1. Field of the Invention
The present invention relates to an electrolumnescence display device comprising electroluminescence elements and thin film transistors.
2. Description of Prior Art
In recent years, electroluminescence (referred to herein after as xe2x80x9cELxe2x80x9d) display devices comprising EL elements have gained attention as potential replacements for CRTs and LCDs. Research has been directed to the development of EL display devices using, for example, thin film transistors (referred to hereinafter as xe2x80x9cTFTxe2x80x9d) as switching elements to drive the EL elements.
FIG. 1A is a plan view showing a display pixel of an organic EL display device. FIG. 1B shows a cross-sectional view taken along line Axe2x80x94A of FIG. 1A while FIG. 1C shows a cross-sectional view taken along line Bxe2x80x94B of FIG. 1A.
As shown in these drawings, a display pixel 20 is formed in a region surrounded by a gate line GL and a data line DL. A first TFT serving as a switching element is disposed near an intersection of those lines. The source of the TFT 1 simultaneously functions as a second capacitor electrode 3 such that, together with a first capacitor electrode 2, it forms a capacitor 8. The source is connected to a gate electrode 15 of a second TFT 4 that drives the organic EL element. The source of the second TFT 4 contacts with an anode 6 of the organic EL element, while the drain of the TFT 4 is connected to a power source line (power source line) VL.
The first capacitor electrode 2, which is made of a material such as chromium, overlaps, over a gate insulating film 7, the second capacitor electrode 3 integral with the source of the first TFT 1. The first capacitor electrode 2 and the second capacitor electrode 3 together store charges with the gate insulating film 7 being interposed therebetween as a dielectric layer. The storage capacitors 8 serves to retain voltage applied to the gate electrodes 15 of the second TFT 4.
The first TFT 1, the switching TFT, will now be described.
First gate electrodes 11 made of refractory metal such as chromium (Cr) or molybdenum (Mo) are formed on a transparent insulator substrate 10 made of quartz glass, non-alkali glass, or a similar material. As shown in FIG. 1A, the first gate electrodes 11 are integrally formed with the gate line GL such that a plurality of these electrodes extend from the gate line GL in the vertical direction in parallel with each other.
Referring to FIG. 1B, the first capacitor electrode 2 formed in the same process as that of the first gate electrodes 11 is provided to the right side of the first gate electrodes 11. This first capacitor electrode 2, which constitutes the storage capacitor 8, has an enlarged portion between the first TFT 1 and the second TFT 4 as shown in FIG. 1A and is integral with a storage capacitor line CL extending therefrom in the directions.
A first active layer 12 composed of poly-silicon (referred to hereinafer as xe2x80x9cp-Sixe2x80x9d) film is formed on the gate insulating film 7. The first active layer 12 is of a so-called LDD (Lightly Doped Drain) structure. Specifically, low-concentration regions are formed on both sides of the gate.
Source and drain regions, which are high-concentration regions, are further disposed on the outboard sides of the low-concentration regions. On the first active layer 12, a stopper insulating film 13 made of Si oxidation film is formed so as to prevent ions from entering the first active layer 12.
An interlayer insulating film 14 formed by sequential lamination of a SiO2 film, a SiN film, and a SiO2 film is provided on the entire surface over the gate insulating film 7, the active layer 12, and the stopper insulating film 13. The data line DL which functions as a drain electrode is electrically connected, through a contact hole C1 formed in the interlayer insulating film 14, to the drain in the active layer 12. A planarizing insulating film 18 made, for example, of an insulating organic resin is also formed over the entire surface for planarization.
In EL display devices which are driven by an electric current, the EL layers must have a uniform thickness.
Otherwise, current concentration may occur in a portion of the layer having thinner thickness. Thus, a significantly high level of planarity is required at least in portions where the EL elements are to be formed, and therefore the above-described planarizing film 18 made of a material having fluidity prior to hardening is employed.
The second TFT 4 which drives the organic EL element will be described with reference to FIGS. 1A and 1C.
On the insulating substrate 10, second gate electrodes 15 made of the same material as the first gate electrodes 11 are provided, and a second active layer 16 is further formed on the gate insulating film 7. Then, a stopper insulating film 17 is formed on the second active layer 16 in a manner similar to the above-mentioned stopper insulating film 13.
Intrinsic or substantially intrinsic channels are formed in the second active layer 16 above the gate electrodes 15, and source and drain regions are formed on respective sides of these channels by doping p-type impurities, thereby constituting a p-type channel TFT.
The above-described interlayer insulating film 14 is provided on the entire surface over the gate insulating film 7 and the second active layer 16, and the power source line VL is electrically connected, through a contact hole C2 formed in the interlayer insulating film 14, to the drain in the active layer 16. Further, the planarizing film 18 is formed over the entire surface, such that the source is exposed through a contact hole C3 formed in the planarizing film 18 and the interlayer insulating film 14. A transparent electrode made of ITO (Indium Tin Oxide) that contacts the source through this contact hole C3, namely, the anode 6 of the organic EL element 20, is formed on the planarizing insulating film 18.
The organic EL element 20 is formed by laminating, in order, the anode 6, an emissive element layer EM comprising a first hole transport layer 21, a second hole transport layer 22, an emissive layer 23 and an electron transport layer 24, and a cathode 25 made of a magnesium-indium alloy. The cathode 25 is substantially disposed over the entire surface of the organic EL elements.
The principle and operation for light emission of the organic EL element is as follows. Holes injected from the anode 6 and electrons injected from the cathode 25 recombine in the emissive layer 23, to thereby excite organic molecules constituting the emissive layer 23, thereby generating excitons. Through the process in which these excitons undergo radiation until deactivation, light is emitted from the emissive layer. This light radiates outward through the transparent anode via the transparent insulator substrate and resultant light emission is observed.
In this way, electric charge corresponding to the display data and applied via the source S of the first TFT 1 is accumulated in the storage capacitor 8 and applied to the gate electrodes 15 of the second TFT 4. According to this voltage, a current is applied to the organic EL element via the second TFT 4 and the organic EL element emits light by the light emitting principle as described above.
Active research of the above-described EL elements is expected continue, and EL display devices with a high yield rate are required. Further, to achieve high resolution, the size of a display pixel must be minimized so that a maximum number of display pixels can be efficiently fabricated into a display pixel region having a limited size.
In the current art, when a specific attention is drawn to one display pixel region as shown in FIG. 1A, a significant number of points where the conductive layers intersect are observed. Specifically, each display pixel includes four intersections, namely, an intersection between the gate line GL and the data line DL, an intersection between the gate line GL and the power source line VL, an intersection between the storage capacitor line CL and the data line DL, and an intersection between the storage capacitor line CL and the power source line VL. This results in the number of intersections corresponding to the number obtained by four times the number of display pixels for the whole panel.
In these intersections, however, short circuit or degradation of voltage withstanding characteristics tends to occur, thereby deteriorating display characteristics. In particular, when there is current leakage from the intersections with the power source line VL, brightness of the EL element decreases because the power source line VL serves as a power source line for supplying a current to the EL element.
The present invention was made in light of the above described disadvantages, and aims to provide a solution by providing a semiconductor layer at an intersection of and between a first line and a second line, which are disposed in a matrix so as to surround the display pixel.
The provided semiconductor layer is a film with relatively high resistance when the layer contains impurities of low concentration or contains substantially no impurities. Thus, when the semiconductor layer is interposed between the first and second lines disposed in a matrix, the voltage withstanding characteristics of both the first and the second lines can be enhanced. Further, since the semiconductor layer is temporarily formed between the first and second line layers, if the semiconductor layer is then removed by etching, the surface of the lines positioned above and under the semiconductor layer, especially the surface of the lower layer, is exposed to an etchant. This may result in characteristics deterioration such as increased line resistance due to formation of a oxidation film on the surface or short circuit. According to the present invention, however, the semiconductor layer is not removed by etching and remains between the layers, such that characteristics deterioration can be prevented.
The present invention is further characterized in that a semiconductor film constituting an active layer of a thin film transistor is provided at the intersection of the gate line and the power source line.
By providing a semiconductor layer formed in the same process as that of forming a semiconductor layer for a thin film transistor at the intersection of the gate line and the power source line VL, voltage withstanding characteristics of the gate line GL and the power source line VL can be enhanced.
The present invention is also characterized in that, in a structure in which the power source line and the data line extend so as to be adjacent to each other, a semiconductor film which constitutes an active layer of a thin film transistor is disposed at a first intersection between the data line and the gate line and in a second intersection between the power source line and the gate line, such that this semiconductor film integrally extends in a region between the first intersection and the second intersection and functions as a common interline insulating protective film.
When individual semiconductor films are provided for the first and the second intersections, the data line DL and the power source line VL must be spaced apart from each other so as to separate these semiconductor films. According to the present invention in which a semiconductor film is integrally formed so as to extend from the first intersection to the second intersection, such spacing is not required, thereby reducing the gap between these lines.
The present invention is further characterized in that, in an EL display device comprising a storage capacitor line which intersects the power source line and overlaps an upper layer electrode which extends from a second conductive region of the first thin film transistor to thereby form a storage capacitor, a semiconductor film constituting an active layer of a thin film transistor is inserted at an intersection between the storage capacitor line and the power source line.
By providing a semiconductor layer formed in the same process as that of a semiconductor, layer constituting a thin film transistor, especially at the intersection of the storage capacitor line CL and the power source line VL, voltage withstanding characteristics of the storage capacitor line CL and the power source line VL can be improved.
The present invention is also characterized in that, in a structure in which the power source line and the data line extend so as to be adjacent to each other, a semiconductor film is inserted at a third intersection between the data line and the storage capacitor line and at a fourth intersection between the power source line and the storage capacitor line, such that this semiconductor film integrally extends in a region between the third intersection and the fourth intersection and functions as a common interline insulating protective film.
When individual semiconductor films are provided for the third and the fourth intersections, the data line DL and the power source line VL must be spaced from each other so as to separate these semiconductor films. According to the present invention in which a semiconductor film is integrally formed so as to extend from the third intersection to the fourth intersection, such spacing is not required, thereby reducing the gap between the data line DL and the power source line VL.
The present invention is still further characterized in that an insulating layer is formed on the semiconductor films provided at these intersections so as to prevent ions from entering the semiconductor films.
It is thus possible to prevent short circuit or degradation of voltage withstanding characteristics in the above-described intersections to there by maintain display characteristics. Further, since the current applied to the power source line VL will not be decreased by current leaking at the intersections, the original brightness of the EL elements can be preserved.